页数：49页文件大小：429.8 KB来源： 硬件描述语言和数字系统设计ppt课件
本课件讲解分频电路的设计方法：先给出2的幂次分频的计数器实现与Verilog描述，再以5分频为例分析常见的双沿触发、占空比不足与综合结果不一致等错误，最后给出奇数次分频获得50%占空比的常用实现思路与仿真波形。
设计硬件描述语言和数字系统设计
设计知识点：
D触发器搭建的16分频电路原理图
比为50%module clk10f (preclk, rst,clk10f); input preclk, rst; output clk10f; reg clk10f; reg [3:0] count; always @ (posedge preclk or posedge rst)if (rst)count <= 4'b0000; else if( count == 4'b0100)count <= 4'b0000; else count <= count + 4'b0001;always @ (posedge preclk or posedge rst)if (rst)clk10f<= 1'b0; else if( count == 4'b0100)clk10f <= ~clk10f; endmodule;10分频的仿真波形
10分频综合的RTL电路图
设占空比为50%module divide5error(rst,clk,clk5); input rst,clk; output clk5; reg clk5; reg [2:0] counter; always @(clk or rst)if (!rst) counter <=3'b000; else if(counter==3'b100)counter <=3'b000; else counter <= counter+1; always @(rst or counter)if (!rst) clk5=1'b0; else if(counter==3'b100)clk5=~clk5; endmodule;从仿真波形上看,满足5分频要求,但是,综合的电路情况是否同样满足呢?
分析-电平触发简化情况module seqorcombin(rst,clk,d,q); input rst,clk; input d; output q; reg q; always @ (clk or rst)if (!rst)q<=1'b0; elseq<=d; Endmodule这是时序逻辑还是组合逻辑?或者你觉得它应该是什么?;(rst,clk,clk5); input rst,clk; output clk5; reg clk5; reg [2:0] counter; always @(posedge clkornegedge clkor negedge rst)if (!rst)counter <=3'b000; else if(counter==3'b100)counter <=3'b000; else counter <= counter+1; always @(rst or counter)if (!rst) clk5=1'b0; else if(counter==3'b100)clk5=~clk5; endmodule9.3.2 error2-5分频电路的两个边沿触发;Leonardo工具综合的电路图综合时报告的ERROR:"E:/divide5_error/divide5error.v", line 28:Error, Always block sensitive to both positive and negative edge of clk andclk can not be synthesized为什么?????(以D触发器说明,上跳沿和下跳沿同时触发可以吗?)always @(posedge clkornegedge clkor negedge rst)if (!rst)q<=1'b0; elseq<=d;module divide5 (rst,clk,clk5); input rst,clk; output clk5; reg clk5; reg [2:0] counter; always @(rst or counter)if (!rst) clk5=1'b0; else if(counter==3'b100)clk5=~clk5;always @(posedge clkor negedge rst)if (!rst)counter <=3'b000; else if(counter==3'b100)counter <=3'b000; else counter <= counter+1; always @(negedge clkor negedge rst)if (!rst)counter <=3'b000; else if(counter==3'b100)counter <=3'b000; else counter <= counter+1; endmodule;(满足5分频占空比为50%的要求)但是综合结果呢?
5分频的Verilog描述-正确方法一//假设占空比为50%moduled5f(clk,rst,clk5f); input clk,rst; output clk5f; wire clk0; wire clk5f; reg [2:0] counter1,counter2; reg clk5f1,clk5f2; assign clk0=~clk;always @(posedge clk or negedge rst)if(!rst)counter1<=0; else if(counter1==3'b100)counter1<=0; else counter1<=counter1+1; always @(posedge clk or negedge rst)if(!rst)clk5f1<=0; elseif((counter1==3'b100)||(counter1==3'b010))clk5f1<=~clk5f1;always @(posedgeclk0or negedge rst)if(!rst)counter2<=0; else if(counter2==3'b100)counter2<=0; else counter2<=counter2+1; always @(posedgeclk0or negedge rst)if(!rst)clk5f2<=0; else if((counter2==3'b100)||(counter2==3'b010))clk5f2<=~clk5f2; assign clk5f=clk5f1|clk5f2; endmodule;分频的仿真波形
分频综合后的电路图
module tb_G5f; reg clk,rst; wire clk5f; always #50 clk=~clk; initialbeginclk=0; rst=1; #5 rst=0; #5 rst=1; end//moduled5f(clk,rst,clk5f); d5f hw(.clk(clk),.rst(rst),.clk5f(clk5f)); endmodule9.4.2 5分频的Verilog描述-正确方法一testbench;5分频的Verilog描述-正确方法二//假设占空比为50%思想方法：能否利用偶数分频2N设计思想（转化为对时钟信号的N计数器设计，在计时器计满一次N时，2N分频信号反向一次）；如果能对奇数分频M进行时钟信号半周期的M计数，那么当计时器计满一次M时，分频信号M反向一次）
进制计数器的Verilog描述要求：对时钟信号clk半周期记一次数
(clk,rst,clk5f);input clk,rst;output clk5f;reg clk5f;reg [3:0] counter1,counter2;reg [4:0] counter_temp, counter;
always @(posedge clk or negedge rst)if(!rst)counter1<=0; else if(counter1==4'b1001)counter1<=0; elsecounter1<=counter1+1;always @(negedge clk or negedge rst)if(!rst)counter2<=0; else if(counter2==4'b1001)counter2<=0; elsecounter2<=counter2+1;always @(counter1 or counter2)counter_temp=counter1+counter2; always @(counter_temp)if(counter_temp>=10)counter=counter_temp-10; elsecounter=counter_temp;always @(rst or counter)if(!rst)clk5f=0; else if(counter==4'b0)clk5f=0; else if(counter==4'b0101)clk5f=1; endmodule;进制计数器方法二-仿真波形
进制计数器方法二-综合结果综合结果：Clk5f会有锁存器产生分析：此处Clk5f需要锁存器。
5进制计数器的Verilog错误表达1modulecounter_error1(clk, rst, counter); input clk, rst; output [2:0] counter; reg [2:0] counter; always @(clk or rst)if (rst) counter <=3'b000; else if (counter==3'b100)counter <= 3'b000; else counter <= counter+ 3'b001; endmodule问题：这是时序逻辑还是组合逻辑?;进制计数器的Verilog错误表达1-仿真波形分析：仿真波形满足要求，但是综合结果呢？
进制计数器的Verilog错误表达1-综合结果综合时报告的Warning:1.Warning,inputclkisneverused.2.Warning,Designcontainscombinatorialloopthroughnetcounter(0),counter(1),counter(2),counter(3).
进制计数器的Verilog错误表达1-综合结果错误原因：过程块使用电平触发方式，在综合时被映射成组合逻辑电路；描述计数器这样的时序逻辑，其敏感量不能采用电平触发方式！！
5进制计数器的Verilog错误表达2modulecounter_error2(clk, rst, counter); input clk, rst; output [2:0] counter; reg [2:0] counter; always @(posedge clk or negedge clk or posedge rst)if (rst)counter<=3'b000; else if(counter==3'b100)counter<= 3'b000; elsecounter<= counter+ 3'b001; endmodule问题：这种描述方式问题出在什么地方？;进制计数器的Verilog错误表达2-仿真波形分析：仿真波形满足要求，但是综合结果呢？
5进制计数器的Verilog错误表达3modulecounter_error3(clk, rst, counter); input clk, rst; output [2:0] counter; reg [2:0] counter; always @(posedge clk or posedge rst)if (rst)counter<=3'b000; else if(counter==3'b100)counter<= 3'b000; elsecounter<= counter+ 3'b001; always @(negedge clk or posedge rst)if (rst)counter<=3'b000; else if(counter==3'b100)counter<= 3'b000; elsecounter<= counter+ 3'b001; endmodule问题：这种描述方式问题出在什么地方？;进制计数器的Verilog错误表达3-仿真波形分析：仿真波形满足要求，但是综合结果呢？
综合工具不能映射成电路，报告的错误信息:Error:electrical errordue tomultiple concurrentassignmentsto ‘counter’.错误原因分析：两块电路的输出信号直接相连，就是多驱动或者线与逻辑，用一般CMOS工艺实现，会使灌电流过大，可能烧坏逻辑门。要实现这样的逻辑，需要用oc门来实现，同时在输出端口应加一个上拉电阻。5进制计数器的Verilog错误表达3
(分频)1.用D触发器做个二分频的电路.又问什么是状态图。（华为）2.请画出用D触发器实现2分频的逻辑电路？（汉王)3.怎样用D触发器、与或非门组成二分频电路？（东信）4.How many flip-flop circuits are needed to divide by16?(Intel) 16分频？5.请用HDL描述5分频电路。（仕兰微电子）
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